//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
//  Version and Release Control Information:
//
//  File Revision       : 129771
//
//  Date                :  2012-05-11 11:13:49 +0100 (Fri, 11 May 2012)
//
//  Release Information : PL401-r0p1-00eac0
//
//------------------------------------------------------------------------------
//  File Purpose        : A Bus matrix write channel router. Stalls connected
//                        slave inetrface write channels until the address
//                        is arbitrated.
//   
//  Key Configuration Details-
//      - Number of connected slave interfaces 1
//      - Acceptance capability 1
//
// Notes on port naming conventions- 
//
//     All AXI point to point connections can be considered a 
//     MasterInterface - SlaveInterface connection. 
//
//     The AXI ports on the NIC400 A3BM are named as follows-  
//
//     *_m<n> suffix to denote a MasterInterface (connect to external AXI slave)
//     *_s0 suffix to denote the SlaveInterface  (connect to external AXI master) 
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Module Declaration
//------------------------------------------------------------------------------

module nic400_switch2_wr_sel_ml1_ysyx_rv32
  (
    // SlaveInterface 0
    // Write Channel
    wdata_s0,
    wstrb_s0,   
    wlast_s0,
    wvalid_s0,
    wready_s0,

    // MasterInterface 
    // Write Channel
    wdata_m,
    wstrb_m,
    wlast_m,
    wvalid_m,
    wready_m
  );

  // ---------------------------------------------------------------------------
  //  parameters
  // ---------------------------------------------------------------------------


  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------

  // MasterInterface 
  // Write Channel
  output  [31:0]    wdata_m;
  output  [3:0]     wstrb_m;
  output            wlast_m;
  output            wvalid_m;
  input             wready_m;
  // SlaveInterfaces
  // Write Channel
  input  [31:0]     wdata_s0;
  input  [3:0]      wstrb_s0;   
  input             wlast_s0;
  input             wvalid_s0;
  output            wready_s0;


  //------------------------------------------------------------------------------
  // Wires 
  //------------------------------------------------------------------------------


  //------------------------------------------------------------------------------
  // Registers 
  //------------------------------------------------------------------------------

  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------


    // Master Interface Write Channel Assignment
    assign wdata_m  = wdata_s0;
    assign wstrb_m  = wstrb_s0;
    assign wlast_m  = wlast_s0;
    assign wvalid_m = wvalid_s0;
    assign wready_s0 = wready_m; 

endmodule

//  --=============================== End ====================================--

